Research on Low Power BIST Based on LFSR Reseeding

With the increasing scale and complexity of internal circuit, function chip is more powerful, but it will bring serious problems to test chip. The power consumption in mode much higher than that normal working mode, especially process built-in self-test, excessive damage circuit under lead failure low vector generation technology reduces by preprocessing set. However, modification set results coverage process. LFSR replaying a common method generating vectors self-test. It can improve faults loading seeds into linear feedback shift register. while improving fault coverage, generate high test. In design for testability (DFT), hot topic low-power combining reseeding with technology. Aiming at problem caused this paper proposes based on reseeding. On basis studying influence dynamic consumption, correlation between seed analyzed deeply. A model optimization Hamming distance sorting proposed realize algorithm. Combined technology, generator designed. simulation ISCAS85 ISCAS89. experimental show total number storage bits reduced 64.39%, average 97.42%, area overhead 4.32%, 44.21%. Compared other schemes, has some comprehensive advantages reducing bits, consumption.